1. Field of the Invention
The present invention is related to pipelined central processing units typical of the mainframe class of computer systems. In particular, the present invention provides a design allowing interlocking of the pipeline of a central processing unit in a selected state based on the validity of other pipeline states under microprogram control.
2. Description of Related Art
Modern data processing machines typically have an instruction processing unit which includes a number of stages in a pipeline configuration. Using a pipeline of a number of stages for execution of instructions allows the machine to overlap processing of more than one instruction at a time in the instruction processing unit. The number of stages of a given instruction which are performed before the next instruction in the instruction stream begins processing, is called the pipeline offset. Thus, if stage two of one instruction is performed in parallel with stage one of the following instruction, the pipeline has a one-cycle offset. If stage three of one instruction is performed in parallel with stage one of the following instruction in the instruction stream, the pipeline has a two-cycle offset. The pipeline offset is an important factor defining the speed at which instructions are supplied to the instruction processing unit during normal operation of the computer.
The pipeline offset also defines a state relationship between succeeding operations in the pipeline. Thus, if a dependent instruction requires the completion of a certain process by a previous instruction in the pipeline, the pipeline state relationship defines the timing in which the processing of the previous instruction must complete before beginning the dependent instruction. Some instructions in the pipeline may not be able to meet the timing requirements defined by the pipeline offset. For instance, a dependent instruction may require data or addresses generated in a pipeline stage that is more than the pipeline offset ahead of the dependent instruction. Therefore it is desirable to provide a microcode controlled interlock to the pipeline to delay processing of the dependent instruction in the pipe until the needed process is complete.
Previous techniques for delaying the pipeline to meet edge conditions that could not conform to the pipeline offset included the insertion of idle instructions causing a "no operation" flow within the instruction unit. Thus, if an N-cycle delay is required, N idle flows are inserted. This approach requires a microstore location for the no-op flows. In view of the expense of microstore locations in a high performance mainframe processing machine, this is an undesirable approach to providing a microprogrammable pipeline delay.
The model 5860 mainframe computer manufactured by Amdahl Corporation provides a microprogrammable scratch register interlock (SRI) which allows an execution unit process to factor into the release of the first state of the instruction processing unit pipeline. The pipeline of the 5860 includes five stages designated G--B--L--E--W, where the execution unit processes during the L and E stages. The operation of the SRI is illustrated in diagram in Table 1.
TABLE 1 ______________________________________ ##STR1## ______________________________________
The first instruction designated OP1 in the instruction processing unit creates conditions to interlock the G-state of the second instruction, designated OP2. Thus, as shown in Table 1, OP1 decodes the instruction to set the scratch register interlock in its G-state. The SRI is set in the B-state causing OP2 to delay until the release signal is asserted. OP1 proceeds to the execution unit processing in the L-cycle from which the release signal is generated. When the release signal is generated, OP2 proceeds with processing. This diagram shows the case in which the release signal is asserted in the L-state; it is also possible in the SRI implementation to assert the signal in the E-cycle from the execution unit.
It should be noted that the SRI was not designed into the model 5860 for the delay function shown above. Rather, its original purpose was to allow the execution unit to access a scratch register file which existed in the instruction unit. The delay function was an additional feature provided by the interlock.
The SRI interlock, while it functions suitably for certain conditions, does not provide the flexibility of totally selectable microprogrammable control. In addition, because the interlock requires a process in the execution unit to factor into the release of the first state of the instruction processing unit pipeline, complicated signal processing is required. For instance, the time required to propagate the release signal from the execution unit to the instruction unit could violate cycle time requirements of faster machines. Also, error analysis and maintenance procedures are made more complex with the SRI approach.
Assuming that no cycle time problem existed with the SRI approach, a programmable delay could be created by having a no-op flow instruct the execution unit to assert the release signal as shown in Table 2.
TABLE 2 ______________________________________ ##STR2## ______________________________________
Table 2 illustrates a pipeline in which the states are designated D--A--B--X--W, where the execution unit performs in the X stage only. Thus, the first instruction, designated NO-OP, would set the SRI in its A cycle, interlock the D-stage in its B-cycle and generate the release signal in its X-cycle from the execution unit. If the NO-OP flow of Table 2 could be used to perform some useful work other than merely setting the SRI, it might be a suitable approach to implementing a programmable delay. However, the exposure to cycle time violations that arise from using an execution unit process in the release of an instruction processing unit stage, make this type of interlock risky. Further, for a pipeline that includes a number of stages preceding the stage during which the execution unit processes the instruction, the offset of the SRI type interlock becomes more inflexible.